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Adding a new dimension to wireless device packaging
Embracing a range of technologies, 3D device stacking, also known as
'system in package' (SiP), is literally, adding a new dimension to the
products offered to the wireless marketplace. Smartphones, PDAs
and similar portable, complex wireless devices are the principle
drivers of advanced microelectronic packaging technology. The
challenge to squeeze ever more performance and functionality into such
a small space would never have been taken up with such fervour if it
wasn't for these high volume markets. But the RF component,
critical to wireless products, is adding a dimension of its own.
For the past decade the 'system on chip' (SoC) methodology has succeeded in integrating analogue, mixed signal and digital circuitry into a single die. Some manufacturers have even overcome the notoriously difficult challenge of integrating RF components, with 'single-chip' handsets now a possibility, though not widely regarded as commercially viable. Expanded feature sets, especially those requiring multiple radios, have prompted renewed efforts to find multichip packaging solutions.
Different applications are trending towards different packaging solutions, ranging from 3D stacked die and stacked packages, to side-by-side packages, and wafer-level packaging. There are technical issues to be solved, particularly avoiding interference between RF devices. One trend is towards SiPs containing partitioned and individually tested and tuned RF subsystems. Another option is to separate receiver and transmitter elements in separate SiPs to improve isolation. The latest thinking is that the distribution of the various RF transceiver and amplifier elements across different substrates, provides more flexibility and the ability to integrate additional features. In particular, separating the power amplifier from the transceiver circuitry allows greater optimisation in terms of performance, cost and footprint. SiPs allow for mixed technologies, such as digital CMOS and mixed signal/RF biCMOS substrates to be integrated into the same package. This has the advantage of avoiding having to integrate RF circuitry onto a pure CMOS substrate, especially for higher power applications.
Packing in the knowledge
The use of SiPs will typically result in a reduction of the overall footprint. Meanwhile, it is becoming standard to embed the associated passive devices and control circuitry in the SiP substrate. It looks like the stand alone RF front end device is no longer a preferred option.
Device packaging is becoming more complex, more important and more costly. This specialist knowledge and capability is going to be increasingly in demand, not only by wireless systems houses designing their own SoCs and SiPs, but also by independent device manufacturers, fabless IC and semiconductor IP vendors, and foundries.
For the past decade the 'system on chip' (SoC) methodology has succeeded in integrating analogue, mixed signal and digital circuitry into a single die. Some manufacturers have even overcome the notoriously difficult challenge of integrating RF components, with 'single-chip' handsets now a possibility, though not widely regarded as commercially viable. Expanded feature sets, especially those requiring multiple radios, have prompted renewed efforts to find multichip packaging solutions.
Different applications are trending towards different packaging solutions, ranging from 3D stacked die and stacked packages, to side-by-side packages, and wafer-level packaging. There are technical issues to be solved, particularly avoiding interference between RF devices. One trend is towards SiPs containing partitioned and individually tested and tuned RF subsystems. Another option is to separate receiver and transmitter elements in separate SiPs to improve isolation. The latest thinking is that the distribution of the various RF transceiver and amplifier elements across different substrates, provides more flexibility and the ability to integrate additional features. In particular, separating the power amplifier from the transceiver circuitry allows greater optimisation in terms of performance, cost and footprint. SiPs allow for mixed technologies, such as digital CMOS and mixed signal/RF biCMOS substrates to be integrated into the same package. This has the advantage of avoiding having to integrate RF circuitry onto a pure CMOS substrate, especially for higher power applications.
Packing in the knowledge
The use of SiPs will typically result in a reduction of the overall footprint. Meanwhile, it is becoming standard to embed the associated passive devices and control circuitry in the SiP substrate. It looks like the stand alone RF front end device is no longer a preferred option.
Device packaging is becoming more complex, more important and more costly. This specialist knowledge and capability is going to be increasingly in demand, not only by wireless systems houses designing their own SoCs and SiPs, but also by independent device manufacturers, fabless IC and semiconductor IP vendors, and foundries.
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